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PT6302 VFD Driver/Controller IC with Character RAM
DESCRIPTION
PT6302 is a dot matrix VFD Driver/Controller IC utilizing CMOS Technology specially designed to display characters, numerals, and symbols. PT6302 provides 35 dot matrix, 2 additional segment drivers and 16 grid drivers. 248 types of character data (CGROM), 8 types of character data (CGRAM), 16 display digits x 2 bits symbol data, 16 display digits x 8 bits register for character data display and 2 general output bits for static operation are provided. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages.
FEATURES
* * * * * CMOS technology Logic power supply: VDD=3.3V10% or 5.0V10% VFD drive power supply: VEE=-20V to -35V Built-in oscillation circuit (External RC) One-byte instruction execution (not including Data Write to RAM) * Microcontroller interface * Display contents: - Character generator ROM (CGROM): 5x7 Dots (248 Character data types) - Character generator RAM (CGRAM): 5x7 Dots (8 Character data types) - Additional data RAM (ADRAM): 16 Display digits x 2 Bits (Symbol data) - Data control RAM (DCRAM): 16 Display digits x 8 Bits (Character data display register) - General output port: 2 bits (Static operation) * Display control function: - Display digits: 9 to 16 digits - Display duty (Contrast adjustment): 8 stages - All display lights: ON/OFF mode
APPLICATIONS
* Microcontroller peripheral device * Audio/Video equipment
BLOCK DIAGRAM
Tel: 886-66296288Fax: 886-29174598 http://www.princeton.com.tw2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6302
APPLICATION CIRCUIT
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ORDER INFORMATION
Valid Part Number PT6302LQ-001 PT6302LQ-002 PT6302LQ-003 PT6302LQ-005 PT6302LQ-006 PT6302LQ-007 Package Type 64 pins, LQFP 64 pins, LQFP 64 pins, LQFP 64 pins, LQFP 64 pins, LQFP 64 pins, LQFP Top Code PT6302LQ-001 PT6302LQ-002 PT6302LQ-003 PT6302LQ-005 PT6302LQ-006 PT6302LQ-007
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name SG5 to SG35 SG4 to SG1 GR1 to GR16 VEE VSS OSCI OSCO RSTB CSB CLKB DIN VDD P1 to P2 AD2 to AD1 V2.1 I/O O O I O I I I I O O Description Segment driver output pin Grid driver output pin Power supply Ground pin Oscillator input pin Oscillator output pin Reset input pin When this pin is set to "LOW", all functions are initialized. Chip select input pin When this pin is set to "High" Level, the serial data transfer is disabled. Shift clock input pin The serial data is shifted at the rising edge of CLKB. Serial data input pin Positive power supply General purpose output pin Segment driver output pin 3 Pin No. 1 ~ 31 64 ~ 61 32 ~ 47 48 49 50 51 52 53 54 55 56 57 ~ 58 59 ~ 60 August 2010
PT6302
INPUT & OUTPUT CONFIGURATION
LOGIC INPUT PINS
LOGIC OUTPUT PINS
DRIVER OUTPUT PINS
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FUNCTION DESCRIPTION
OSCILLATION CIRCUIT
An oscillation circuit may be constructed by connecting external Resistor (R1) and Capacitor (C1) between the oscillator pins -- OSCO and OSCI. The RC time constant depends on the value of VDD voltage used. The target oscillation frequency is 2MHz. Please refer to the diagram below.
RESET FUNCTION
The Reset Function is enabled when the RSTB Pin is set to "Low" Level. All functions are initialized. The initial status of the various functions is given below: 1. Address of each RAM: Address "00"H 2. Data of each RAM: All contents are undefined. 3. General Output Ports: All General Output Ports are set to "LOW". 4. Display Digit: 16 Digits 5. Contrast Adjustment: 8/16 6. All Display Lights: OFF Mode 7. Segment Output: All Segment Outputs are set to "LOW". 8. AD Output: All AD Outputs are set to "LOW". The RSTB Pin may be connected to either the microcontroller or an external Resistor and capacitor. For an external RC connection, please refer to the diagram below.
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After reset, the PT6302 must be set according to the Initial Setting Flowchart shown below.
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RELATIONSHIP BETWEEN SEGMENT DRIVERS SGN AND ADN (ONE DIGIT)
The following diagram best describes the relationship between the Segment Drivers -- SGn and ADn.
C0 AD1 C1 AD2 C0 SG1 C5 SG6 C10 SG11 C15 SG16 C20 SG21 C25 SG26 C30 SG31
DATA IS WRITTEN BY ADRAM. THIS CORRESPONDS TO THE 2ND BYTE
C1 SG2 C6 SG7 C11 SG12 C16 SG17 C21 SG22 C26 SG27 C31 SG32
C2 SG3 C7 SG8 C12 SG13 C17 SG18 C22 SG23 C27 SG28 C32 SG33
C3 SG4 C8 SG9 C13 SG14 C18 SG19 C23 SG24 C28 SG29 C33 SG34
C4 SG5 C9 SG10 C14 SG15 C19 SG20 C24 SG25 C29 SG30 C34 SG35
DATA IS WRITTEN BY THE CGRAM. THIS CORRESPONDS TO THE 2ND BYTE
DATA IS WRIITEN BY THE CGRAM THIS CORRESPONDS TO THE 6TH DATA IS WRITTEN BY THE CGRAM THIS CORRESPONDS TO THE 5TH DATA IS WRITTEN BY THE CGRAM THIS CORRESPONDS TO THE 4TH
DATA IS WRIITEN BY THE CGRAM THIS CORRESPONDS TO THE 3RD BYTE.
DATA TRANSFER
The Display Control Command and the data are written by an 8-bit serial data transfer. Please refer to the Write Timing Diagram below.
Note: When data is written into the RAM (DCRAM, ADRAM, CGRAM) in a continuous manner, the address are automatically incremented. Therefore it is not necessary to specify the first byte of the 2nd and later bytes when writing the RAM data.
When the CSB pin is set to "LOW" Level, data transfer operation is enabled. 8 bits of data are sequentially inputted into the DIN Pin (LSB first). The shift clock is inputted into CLKB pin and the shift register reads the data at rising edge of the shift clock. The internal load signals are automatically generated and the data is written to each register and RAM. Thus, it is not necessary to input load signals externally. When the CSB Pin is set to "HIGH" Level, the data transfer operation is disabled. The data input when the CSB Pin changes from "HIGH" to "LOW" is recognized in 8-bit units. V2.1 7 August 2010
PT6302
COMMANDS
The following are the list of commands issued by PT6302. When data is written into the RAM (DCRAM, CGRAM, or ADRAM) in a continuous manner, the addresses are automatically incremented internally. It is therefore not necessary to specify the first byte.
NO. 1 COMMAND DCRAM DATA WRITE LSB B0 B1 X0 X1 FIRST BYTE B2 B3 B4 X2 X3 1 B5 0 B6 0 MSB B7 0 LSB B0 C0 C0 C1 2 CGRAM DATA WRITE X0 X1 X2 * 0 1 0 0 C2 C3 C4 3 4 5 6 7 ADRAM DATA WRITE GENERAL OUTPUT PORT SET DISPLAY DUTY SET NO. OF DIGITS SET ALL LIGHTS ON/OFF TEST MODE X0 P1 D0 K0 L 0 X1 P2 D1 K1 H 0 X2 * D2 K2 * 0 X3 * * * * * 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 C0 B1 C1 C5 C6 C7 C8 C9 C1 SECOND BYTE B2 B3 B4 C2 C3 C4 C10 C11 C12 C13 C14 * C15 C16 C17 C18 C19 * C20 C21 C22 C23 C24 * B5 C5 C25 C26 C27 C28 C29 * B6 C6 C30 C31 C32 C33 C34 * MSB B7 C7 * * * * * * 2ND BYTE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE
Notes: 1. The Test Mode is not a user function, but an IC internal function 2. *=Not relevant 3. Xn=RAM address bit, n = 0 to 3 4. Cn=RAM character code bit, n=0 to 34 5. Pn=General output port status bit, n=1 to 2 6. Dn=Display duty bit, n=0 to 2 7. Kn=Number of digits bit, n=0 to 2 8. H=All lights on 9. L=All lights off
DATA CONTROL RAM (DCRAM) DATA WRITE COMMAND
The DCRAM Data Write Command is used to specify the address of the DCRAM and writes the character code of the CGROM and CGRAM. The DCRAM consists of 4 address bits which are used to store the CGRAM & CGROM character codes. The character codes specified by the DCRAM is converted to a 5 x 7 dot matrix character pattern via the CGROM and CGRAM. The DCRAM can store up to 16 characters. The DCRAM Data Write Command Format is shown below. LSB B0 X0 LSB B0 C0 B1 X1 B2 X2 B3 X3 B4 1 B5 0 B6 0 MSB B7 0 MSB B7 C7 DCRAM Data Write Mode is selected and the DCRAM Address is specified. (i.e. DCRAM Address = 0H) CGROM & CGRAM Character Codes are specified. (They are written into the DCRAM Address 0H)
1st Byte (1st)
2nd Byte (2nd)
B1 C1
B2 C2
B3 C3
B4 C4
B5 C5
B6 C6
During a continuous data write operation from one DCRAM Address to the next, it is not necessary to specify the DCRAM address since they are automatically incremented; however, the character code must be specified. Please refer to the information below. 2nd Byte (3rd) LSB B0 C0 B1 C1 B2 C2 B3 C3 B4 C4 B5 C5 MSB B6 B7 C6 C7 8 Character Code of CGRAM & CGROM are specified and written into the DCRAM Address 1H.
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LSB 2nd Byte (4th) B0 C0 LSB B0 C0 LSB B0 C0 B1 C1 B2 C2 B3 C3
: :
MSB B4 C4 B5 C5 B6 C6 B7 C7 MSB B7 C7 MSB B7 C7 Character Code of CGRAM & CGROM are specified and written into the DCRAM Address 2H.
2nd Byte (17th)
B1 C1 B1 C1
B2 C2 B2 C2
B3 C3 B3 C3
B4 C4 B4 C4
B5 C5 B5 C5
B6 C6 B6 C6
Character Code of CGRAM & CGROM are specified and written into the DCRAM Address FH.
2nd Byte (18th)
Character Code of CGRAM & CGROM are specified and rewritten into the DCRAM Address 0 H.
where: 1. X0 (LSB) to X3 (MSB): DCRAM Address Bits (16 Characters) 2. C0 (LSB) to C7 (MSB): CGROM & CGRAM Character Code Bits (256 Characters) Please refer to the table below for the GRID position and DCRAM Address setting relationship. Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GRID Position GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 GR13 GR14 GR15 GR16
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CGRAM DATA WRITE COMMAND
The Character Generator RAM (CGRAM) Data Write Command is used to specify the CGRAM address (00H to 07H) and write the character pattern data. It consists of 3 address bits which is used to store the 5 x 7 dot matrix character patterns. The CGRAM can store up to 8 types of character patterns which may be displayed by specifying the Character Code (DCRAM Address). The CGRAM Data Write Command Format is given below. 1st Byte (1st) LSB B0 X0 LSB 2nd Byte (2nd) B0 C0 LSB 3rd Byte (3rd) B0 C1 LSB 4th Byte (4th) B0 C2 LSB 5th Byte (5th) B0 C3 LSB 6th Byte (6th) B0 C4 B1 C9 B2 C14 B3 C19 B4 C24 B5 C29 B6 C34 B1 C8 B2 C13 B3 C18 B4 C23 B5 C28 B6 C33 B1 C7 B2 C12 B3 C17 B4 C22 B5 C27 B6 C32 B1 C6 B2 C11 B3 C16 B4 C21 B5 C26 B6 C31 B1 C5 B2 C10 B3 C15 B4 C20 B5 C25 B6 C30 MSB B7 0 MSB B7 * MSB B7 * MSB B7 * MSB B7 * 4th Column Data is specified and rewritten into the CGRAM Address 00H. MSB B7 * 5th Column Data is specified and rewritten into the CGRAM Address 00H. 3rd Column Data is specified and rewritten into the CGRAM Address 00H. 2nd Column Data is specified and rewritten into the CGRAM Address 00H. 1st Column Data is specified and rewritten into the CGRAM Address 00H. CGRAM Data Write Mode is selected and the CGRAM Address is specified (i.e. CGRAM Address = 00H).
B1 X1
B2 X2
B3 *
B4 0
B5 1
B6 0
During a continuous data write operation from one CGRAM Address to the next, it is not necessary to specify the CGRAM address since they are automatically incremented; however, the character pattern data must be specified. The 2nd to the 6th character pattern data byte are considered as one data item, therefore 300ns is sufficient value for parameter tDOFF between bytes. Please refer to the information below. LSB 2nd Byte (7th) B0 C0 B1 C5 B2 C10 B3 C15 : : LSB 6th Byte (11th) B0 C4 B1 C9 B2 C14 B3 C19 B4 C24 B5 C29 B6 C34 MSB B7 * 5th Column Data is specified and rewritten into the CGRAM Address 01H. B4 C20 B5 C25 B6 C30 MSB B7 * 1st Column Data is specified and rewritten into the CGRAM Address 01H.
where: 1. X0 (LSB) to X2 (MSB): CGRAM Address Bits (8 Characters) 2. C0 (LSB) to C34 (MSB): Character Pattern Data Bits (35 outputs/digit) V2.1 10 August 2010
PT6302
Please refer below for the CGROM Address and CGRAM Address Setting relationship. HEX 00 01 02 03 04 05 06 07 X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 CGROM Address RAM00(00000000B) RAM01(00000001B) RAM02(00000010B) RAM03(00000011B) RAM04(00000100B) RAM05(00000101B) RAM06(00000110B) RAM07(00000111B)
The CGROM and CGRAM output area placement is given in the table below. C0 C5 C10 C15 C20 C25 C30 C1 C6 C11 C16 C21 C26 C31 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 Area corresponds to the 6th Byte (5th Column) Area corresponds to the 5th Byte (4th Column) Area corresponds to the 4th Byte (3rd Column) Area corresponds to the 3rd Byte (2nd Column) Area corresponds to the 2nd Byte (1st Column)
Note: The Character Generator ROM (CGROM) consists of 8 CGROM Address bits generating 5 x 7 dot matrix character patterns. It can store up to a maximum of 248 types of character patterns.
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ADRAM DATA WRITE COMMAND
The Additional Data RAM (ADRAM) consists of 4 address bits used to store the symbol data. It can store up to 2 types of symbol patterns per digit. The symbol data specified by the ADRAM is directly outputted. The terminals to which the ADRAM data are outputted may be used as a cursor. The ADRAM command format is given below. LSB 1st Byte (1st) B0 X0 LSB 2nd Byte (2nd) B0 C0 B1 C1 B2 * B3 * B4 * B5 * B6 * B1 X1 B2 X2 B3 X3 B4 1 B5 1 B6 0 MSB B7 0 MSB B7 * Symbol Data is specified and written into the ADRAM Address 0H. ADRAM Data Write Mode is selected and the ADRAM address is specified. (i.e. ADRAM Address = 0H)
During a continuous data write operation from one ADRAM Address to the next, it is not necessary to specify the ADRAM address since they are automatically incremented; however, the symbol data must be specified. Please refer to the information below. LSB MSB 2nd Byte B0 B1 B2 B3 B4 B5 B6 B7 Symbol Data is specified and written into the ADRAM (3rd) Address 1H. C0 C1 * * * * * * LSB 2nd Byte (4th) B0 C0 B1 C1 B2 * B3 * : : B3 * B4 * B5 * B6 * MSB B7 * Symbol Data is specified and written into the ADRAM Address 2H.
LSB 2nd Byte (17th) B0 C0 LSB 2nd Byte (18th) B0 C0 B1 C1 B2 * B3 * B4 * B5 * B6 * B1 C1 B2 * B4 * B5 * B6 *
MSB B7 * MSB B7 * Symbol Data is specified and rewritten into the ADRAM Address 0H. Symbol Data is specified and written into the ADRAM Address FH.
where: 1. X0 (LSB) to X3 (MSB): ADRAM address bits (16 Characters) 2. C0 (LSB) to C1 (MSB): Symbol data bits (2 symbol data per digit)
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Please refer to the table below for the GRID and ADRAM Address relationship. HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GRID Position GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 GR13 GR14 GR15 GR16
GENERAL OUTPUT PORT SET COMMAND
The General Output Port Set Command is used to specify the general output port status. The general output port is used to control other input/output devices as well as turn on the LED Display. When the general output port is set to "HIGH", the output is equivalent to the VDD voltage. When the general output port is set to "LOW" Level, the output becomes ground potential. The command format is given below. LSB 1st Byte B0 B1 B2 B3 * B4 0 P1 P2 * where: 1. P1, P2: General output port 2. *=Not relevant MSB B5 0 B6 1 B7 0 A General Output Port is selected and the output status is specified.
The following table shows the data setting in relation to the Status of the General Output Port P1 0 1 0 1 P2 0 0 1 1 General Output Port Display Status P1 ="LOW", P2="LOW" (see note 1) P1="HIGH", P2="LOW" P1="LOW", P2="HIGH" P1="HIGH", P2="HIGH"
Note: The state when the power is applied or when the RSTB is inputted.
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DISPLAY DUTY SET COMMAND
The Display Duty Set Command is used to write the display duty value to the duty cycle register. Using a 3-bit data, the display duty adjusts the contrast in 8 stages. When the power is turned ON or when the RSTB signal is inputted, the duty cycle register value is set to "0". It is advisable to always execute this command before turning on the display, after which the desired duty value may be set. The command format is given below. LSB MSB 1st Byte B0 B1 B2 B3 B4 B5 B6 B7 Display Duty Set Mode is selected and the duty value is specified. D0 D1 D2 * 1 0 1 0 where: 1. D0 (LSB) to D2 (MSB): Display duty data bits (8 stages) 2. *=Not relevant The Relationship between the Setup Data and the Controlled GRID Duty is given in the table below. HEX D2 D1 D0 GRID Duty The state when the Power is turned ON or when 0 0 0 0 8/16 the RSTB signal is inputted 1 0 0 1 9/16 2 0 1 0 10/16 3 0 1 1 11/16 4 1 0 0 12/16 5 1 0 1 13/16 6 1 1 0 14/16 7 1 1 1 15/16
NUMBER OF DIGITS SET COMMAND
The Number of Digits Set Command is used to write the number of display digits into the display digit register. Using a 3-bit data, the Number of Digits Set Command can display 9 to 16 digits. When the power is turned ON or when the RSTB signal is inputted, the value is set to "0". It is advisable to always execute this command before the turning on the display. The command format is given below. LSB MSB 1st Byte The Number of Digits Set Mode is selected and the B0 B1 B2 B3 B4 B5 B6 B7 number of digit value is specified. K0 K1 K2 * 0 1 1 0 The table below shows the relationship between the setup data and the controlled GR. HEX K2 K1 K0 Number of Digits of GR The state when the Power is turned ON or 0 0 0 0 GR1 ~ GR16 when the RSTB signal is inputted. 1 0 0 1 GR1 ~ GR9 2 0 1 0 GR1 ~ GR10 3 0 1 1 GR1 ~ GR11 4 1 0 0 GR1 ~ GR 12 5 1 0 1 GR1~ GR13 6 1 1 0 GR1~ GR14 7 1 1 1 GR1~ GR15
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DISPLAY LIGHT SET COMMAND
The Display Light Set Command is used to turn all display lights ON or OFF. All Display Lights ON Mode is primarily used for testing the display. The All Display Light OFF Mode is used for the blinking display and to prevent any malfunction when the power is turned ON. The general output port cannot be controlled by this command. The command format is given below. LSB MSB 1st Byte B0 L B1 H B2 * B3 * B4 1 B5 1 B6 1 B7 0 The Display Light Set Command is selected.
where: 1. L=All display lights are turned off 2. H=All display lights are turned on 3. *=Not relevant The table below shows the SG and AD Display Status in relation to the Display Light Set Command data.
L 0 1 0 1 H 0 0 1 1 SG and AD Display State Normal Display Mode All Outputs ="LOW" All Outputs ="HIGH" All Outputs = "HIGH" The state when the power is applied or when the RSTB signal is inputted All Display Light ON Mode has the first priority.
RECOMMENDED SOFTWARE FLOWCHART
Notes: 1. Display light active mode (ex. 0111XX00B) 2. Test mode off (ex. 1000X000B)
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage 1 Supply voltage 2 Input voltage Power dissipation Output current 1 Output current 2 Output current 3 Output current 4 Operating temperature Storage temperature Symbol VDD VEE VIN PD IO1 IO2 IO3 IO4 Topr Tstg Condition Ta 25 GR1 to GR16 AD1 to AD2 SG1 to SG35 P1 to P2 Rating -0.3 to 6.5 -35 to VDD+0.3 -0.3 to VDD+0.3 541 -40 to 0 -20 to 0 -10 to 0 -4.0 to 4.0 -40 to +85 -65 to +150 Unit V V V mW mA mA mA mA
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage 1 Supply voltage 2 High level input voltage Low level input voltage CLKB frequency Oscillation frequency Symbol VDD VEE VIH Power supply voltage=5V Power supply voltage=3.3V Power supply voltage=5V All input pins except OSCI. Power supply voltage=3.3V All input pins except OSCI. Power supply voltage=5V All input pins except OSCI. Power supply voltage=3.3V All input pins except OSCI. Power supply voltage=5V Power supply voltage=3.3V Power supply voltage=5V R1=3.3K, C1=47pF Power supply voltage=3.3V R1=3.3K, C1=39pF Power supply voltage=5V DIGIT=1 to 16, R1=3.3K, C1=47pF Power supply voltage=3.3V DIGIT=1 to 16, R1=3.3K, C1=39pF Power supply voltage=5V Power supply voltage=3.3V Power supply voltage=5V Power supply voltage=3.3V Condition Min. 4.5 3.0 -35 -35 0.7VDD 0.8VDD 1.5 1.5 183 183 200 200 -40 -40 Typ. 5.0 3.3 2.0 2.0 244 244 Max. 5.5 3.6 -20 -20 0.3VDD 0.2VDD 1.0 1.0 2.5 2.5 305 305 85 85 Unit V V V V V V V V MHz MHz MHz MHz Hz Hz s
VIL fc fosc
Frame frequency RSTB input time Operating temperature
fFR tRSON Topr
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DC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VEE=-35V, Ta=-40 to +85)
Parameter High level input voltage Symbol VIH Condition VDD=5.010% CSB, CLKB, DIN, RSTB VDD=3.310% CSB, CLKB, DIN, RSTB VDD=5.010% CSB, CLKB, DIN, RSTB VDD=3.310% CSB, CLKB, DIN, RSTB VDD=5.010% CSB, CLKB, DIN, RSTB; VIH=VDD VDD=3.310% CSB, CLKB, DIN, RSTB; VIH=VDD VDD=5.010% CSB, CLKB, DIN, RSTB; VIL=0V VDD=3.310% CSB, CLKB, DIN, RSTB; VIL=0V VDD=5.010% GR1 to GR16; IOH=-30mA VDD=3.310% GR1 to GR16; IOH=-30mA VDD=5.010% AD1 to AD2, IOH=-15mA VDD=3.310% AD1 to AD2, IOH=-15mA VDD=5.010% SG1 to SG35, IOH=-6mA VDD=3.310% SG1 to SG35, IOH=-6mA VDD=5.010% P1 to P2, IOH=-5mA VDD=3.310% P1 to P2, IOH=-2.5mA VDD=5.010% GR1 to GR16, AD1 to AD2,SG1 to SG35 VDD=3.310% GR1 to GR16, AD1 to AD2; SG1 to SG35 VDD=5.010% P1, P2, IOL=15mA VDD=3.310% P1, P2, IOL=7.5mA VDD=5.010% VDD, fosc=2MHz, No Load Duty 15/16, DIGIT 1 to 16; All outputs lights ON VDD=3.310% VDD, fosc=2MHz, No Load Duty 15/16, DIGIT 1 to 16; All outputs lights ON VDD=5.010% VDD, fosc=2MHz, No Load Duty 8/16, DIGIT 1 to 9; All outputs lights OFF VDD=3.310% VDD, fosc=2MHz, No Load Duty 8/16, DIGIT 1 to 9; All outputs lights OFF Min. 0.7VDD 0.8VDD -1.0 -1.0 -1.0 -1.0 VDD-1.5 VDD-1.5 VDD-1.5 VDD-1.5 VDD-1.5 VDD-1.5 VDD-1.0 VDD-1.0 Max. 0.3VDD 0.2VDD 1.0 1.0 1.0 1.0 VEE+1.0 VEE+1.0 1.0 1.0 4 3 3 2 Unit V V V V A A A A V V V V V V V V V V V V mA mA mA mA
Low level input Voltage
VIL
High level input current
IIH
Low level input current
IIL
High level output voltage 1
VOH1
High level output voltage 2
VOH2 VOH3
High level output voltage 3
High level output voltage 4
VOH4
Low level output voltage 1
VOL1
Low level output voltage
VOL2
Current consumption 1
IDD1
Current consumption 2
IDD2
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AC CHARACTERISTICS
(Unless otherwise specified, VEE=-35V, Ta=-40 to +85) Parameter Symbol Condition VDD=5.0V+10% CLKB cycle time fc VDD=3.3V+10% VDD=5.0V+10% CLKB pulse width tCW VDD=3.3V+10% VDD=5.0V+10% DIN setup time tDS VDD=3.3V+10% VDD=5.0V+10% DIN hold time tDH VDD=3.3V+10% VDD=5.0V+10% CSB setup time tCSS VDD=3.3V+10% VDD=5.0V+10% R1=3.3K, C1=47pF CSB hold time tCSH VDD=3.3V+10% R1=3.3K, C1=39pF VDD=5.0V+10% CSB wait time tCSW VDD=3.3V+10% VDD=5.0V+10% R1=3.3K, C1=47pF Data processing time tDOFF VDD=3.3V+10% R1=3.3K, C1=39pF VDD=5.0V+10% When the RSTB signal is externally inputted from the microcontroller. RSTB pulse width tWRSTB VDD=3.3V+10% When the RSTB signal is externally inputted from the microcontroller. VDD=5.0V+10% DIN wait time tRSOFF VDD=3.3V+10% VDD=5.0V+10% Ci=100pF, tR=20% to 80% tR VDD=3.3V+10% Ci=100pF, tR=20% to 80% All outputs slew rate VDD=5.0V+10% Ci=100pF, tF=80% to 20% tF VDD=3.3V+10% Ci=100pF, tF=80% to 20% VDD=5.0V+10% Mounted in the Unit VDD rise time tPRZ VDD=3.3V+10% Mounted in the Unit VDD=0V VDD off time tPOF Mounted in the Unit Min. 1.0 1.0 300 300 300 300 300 300 300 300 16 16 300 300 8 8 300 Max. Unit s s ns ns ns ns ns ns ns ns s s ns ns s s ns
300 300 300 100 100 5.0
4.0 4.0 4.0 4.0 -
ns ns ns s s s s
s ms
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TIMING CHARACTERISTICS
Parameter High level input voltage Low level input voltage Symbol VIH VIL VDD=3.3V10% 0.8VDD 0.2VDD VDD=5.010% 0.7VDD 0.3VDD
DATA TIMING
RESET (RSTB) TIMING
OUTPUT TIMING
DIGIT OUTPUT TIMING (16-DIGIT DISPLAY, DUTY= 15/16)
where: T=8/fosc V2.1 19 August 2010
PT6302
PT6302-001 CHARACTER FONT TABLE
V2.1
20
August 2010
PT6302
PT6302-002 CHARACTER FONT TABLE
V2.1
21
August 2010
PT6302
PT6302-003 CHARACTER FONT TABLE
V2.1
22
August 2010
PT6302
PT6302-005 CHARACTER FONT TABLE
V2.1
23
August 2010
PT6302
PT6302-006 CHARACTER FONT TABLE
V2.1
24
August 2010
PT6302
PT6302-007 CHARACTER FONT TABLE
V2.1
25
August 2010
PT6302
PACKAGE INFORMATION
64 PINS, LQFP
Symbol A A1 A2 b c D D1 E E1 e L L1
Notes: 1. All dimensions are in millimeter 2. Refer to JEDEC MS-022 BE
Min. 0.05 1.35 0.30 0.09
0.45 0
Nom. 1.40 0.35 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.80 BSC 0.60 1.00 REF. 3.5
Max. 1.60 0.15 1.45 0.40 0.16
0.75 7
V2.1
26
August 2010
PT6302 IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw
V2.1
27
August 2010

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